The present invention relates to electrically erasable programmable read only memory (EEPROM) cells using a single transistor for the memory cell.
The number of transistors used in a memory cell has been steadily decreased through improved designs in order to improve the density on a semiconductor memory chip. EEPROM memory cells provide static memory storage through the use of a floating gate transistor. The floating gate stores charge, indicating a digital 1, or has no charge, indicating a digital zero. Typically, a second transistor is required in conjunction with the EEPROM transistor to isolate that transistor from other memory cells when a particular memory cell is being operated upon. The extra transistor is required because of the programming and erase functions which must be provided, in addition to the normal read function.
A number of designs have provided single transistor cells which rely on the Fowler-Nordheim tunneling mechanism to program and erase a floating gate transistor. Such memory cells are sometimes referred to as "flash" memory cells. One such transistor configuration is shown in U.S. Pat. No. 4,698,787, which uses hot electron injection for programming and Fowler-Nordheim tunneling for erasing. The absence of the extra isolated transistor requires certain tricks in being able to program and erase the transistor. In the embodiment shown in the '787 patent, the memory cell transistors are alternately inverted so that their drains and sources are coupled together. Another configuration discussed in a paper entitled "A 5 V-Only 256 K Bit CMOS Flash EEPROM" by Sebastiano D'Arrigo, et al. of Texas Instruments Incorporated presented at the 1989 IEEE International Solid-State Circuits Conference, describes a design which requires a complex combination of voltages for programming transistor cells without affecting previously programmed cells. This includes the biasing of non-selected word lines as well as selected word lines with different voltage levels.
A problem common to the single transistor configurations is that of "over-erasing". When the floating gate transistor is erased, applied voltages establish a strong electric field across the gate and drain regions such that electrons are removed from the floating gate of the transistor. As the electrons are removed, the threshold voltage of the cell decreases. As long as there is a positive potential from the drain to the gate, electrons will continue to be removed, causing excess electrons to be removed. Thus, instead of the floating gate going from a negative to a zero potential, the floating gate goes to a positive potential. Thus, after erasing, an inversion layer will be formed in the channel area of the transistor even though the gate is biased at zero volts. The formation of this channel turns on an unselected cell, causing current to flow, and thus an error, when attempting to read a selected cell which is turned off.